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AD9652 雙路16位310MSPS模數(shù)轉(zhuǎn)換(ADC)方案

文章來(lái)源：更新時(shí)間：2014/12/11 14:30:00

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ADI公司的AD9652是雙路16位取樣速率高達(dá)310MSPS的模數(shù)轉(zhuǎn)換器(ADC),雙路ADC核具有多級(jí)流水線架構(gòu)和輸出誤差修正邏輯,輸入頻率范圍高達(dá)465MHz,極低的噪音-157.6dBFS,SFDR超過(guò)85dBFS,通路間隔離/串?dāng)_90dB,主要用在軍用雷達(dá)和通信,多模式數(shù)字接收器(3G或4G), 測(cè)試測(cè)量和智能天線系統(tǒng).本文介紹了AD9652產(chǎn)品亮點(diǎn)和主要特性,功能框圖,以及評(píng)估板AD-FMCOMMS6-EBZ主要特性,主要元件分布圖,電路圖和PCB元件分布圖.
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.
The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents.

AD9652產(chǎn)品亮點(diǎn):
1. Integrated dual, 16-bit, 310 MSPS ADCs.
2. On-chip buffer simplifies ADC driver interface.
3. Operation from 3.3 V and 1.8 V supplies and a separate digital output driver supply accommodating LVDS outputs.
4. Proprietary differential input maintains excellent signal-to-noise ratio (SNR) performance for input frequencies of up to 485 MHz.
5. SYNC input allows synchronization of multiple devices.
6. Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback.

AD9652主要特性:
High dynamic range
SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)
Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz
NSD = −157.6 dBFS/Hz for small signal at −7dBFS at 70 MHz
90 dB channel isolation/crosstalk
On-chip dithering (improves small signal linearity)
Excellent IF sampling performance
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz
On-chip 3.3 V buffer
Programmable input span of 2 V p-p to 2.5 V p-p (default)
Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer
SYNC input allows multichip synchronization
Total power consumption: 2.16 W
3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs
Serial port control
Energy saving power-down modes
AD9652應(yīng)用:
Military radar and communications
Multimode digital receivers (3G or 4G)
Test and instrumentation
Smart antenna systems

圖1. AD9652功能框圖

評(píng)估板AD-FMCOMMS6-EBZ
The AD-FMCOMMS6-EBZ eval board is a 400MHz to 4.4GHz receiver based on the AD9652 dual 16bit analog to digital converter, the ADL5566 High Dynamic Range RF/IF Dual Differential Amplifier and the ADL5380 quadrature demodulator. This is an I and Q demodulation approach to direct convert (also known as a homodyne or zero IF) receiver architecture. Direct conversion radios perform just one frequency translation compared to a super-heterodyne receiver that can perform several frequency translations. One frequency translation is advantageous because it • Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption • Avoids image rejection issues and unwanted mixing. This topology will provide image rejection and early implementation of the differential signal environment. There is an amplification stage to maintain the full-scale input to the ACD. The local oscillator and ADC clock are on board and share the same reference signal prevent smearing. The form factor is VITA57 compliant and all of the DC power is routed from the data capture board through an FMC connector. This evaluation board demonstrates a high performance receiver signal chain aimed at military and commercial radar using “commercial off the shelf” (COTS) components. The overall circuit has a bandwidth of 220MHz with a pass band flatness of +/_ 1.0 dB. The SNR and SFDR measured at an IF of 145MHz are 64dB and 75dBc, respectively.
The AD-FMCOMMS6-EBZ evaluation board is a 400MHz to 4.4GHz receiver based on the AD9652 dual 16-bit analog to digital converter (ADC), the ADL5566 High Dynamic Range RF/IF Dual Differential Amplifier and the ADL5380 quadrature demodulator. This is an I and Q demodulation approach to direct convert (also known as a homodyne or zero IF) receiver architecture. This topology will provide image rejection and early implementation of the differential signal environment. There is an amplification stage to maintain the full-scale input to the ADC. The local oscillator and ADC clock are on board and share the same reference signal to prevent smearing. The form factor is VITA57 compliant and all of the DC power is routed from the data capture board through an FMC connector. This evaluation board demonstrates a high performance receiver signal chain aimed at military and commercial radar using "commercial off the shelf" (COTS) components. The overall circuit has a bandwidth of 220MHz with a pass band flatness of +/_ 1.0 dB. The SNR and SFDR measured at an IF of 145MHz are 64dB and 75dBc, respectively.

評(píng)估板AD-FMCOMMS6-EBZ主要特性:
RFin: 100MHz to 4GHz
IF: 10-155MHz
SNR: 68dB
SFDR: 78dB
RF input frequency range
- ADL5380: 400MHZ – 6 GHz Demod
- Supports UHF through S-bands and some C-band
AD9652: 16-bit, 310MSPS Dual ADC
- 74dB SNR across 1st Nyquist Zone
- 96dB SFDR
- 155dBFS/Hz noise floor
Integrated LO and on-board Clock with system reference and fanout
Amplifier and Filtering Options on-board
- ADL5566 Amp provides full-scale ADC Input
- AAF remove unwanted wideband noise
I/Q Demodulation
- Image rejection
- Low LO to RF leakage
評(píng)估板AD-FMCOMMS6-EBZ應(yīng)用:
Military radar and communications
Reduced Size Weight and Power (SWaP)
Basestations
Handsets
Broadband instrumentation
Portable instrumentation

http://wiki.analog.com/_media/resources/fpga/xilinx/fmc/fmcomms6/top_view_main_page.png?w=400

圖2. 評(píng)估板AD-FMCOMMS6-EBZ外形圖

圖3. 評(píng)估板AD-FMCOMMS6-EBZ元件分布圖

評(píng)估板AD-FMCOMMS6-EBZ包括:
AD9652 two 16-bit ADC with sampling speeds of up to 310 MSPS
ADL5380, a broadband quadrature I-Q demodulator that covers an RF/IF input frequency range from 400 MHz to 6 GHz.
ADL5566 a high performance, dual differential amplifier optimized for IF and dc applications.
ADP2370 high efficiency, low quiescent current, 800 mA buck (step-down) dc-to-dc converters in small 8-lead, 3 mm × 3 mm LFCSP (QFN) packages.
AD9517-4 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO.
ADF4351 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external loop filter and external reference frequency.
ADM7150 is a low dropout linear regulator that operates from 4.5 V to 16 V and provides up to 800 mA of output current.